Conventional drivers are normally used to drive small loads. It is usually desirable to have a highly controllable current level in the output branch of the driver in a quiescent state, and a high peak current level with input voltage signals having a wide peak-to-peak variation. Accordingly, it is necessary to use a class AB output stage for the driver to provide high peak currents.
Two approaches are currently used to provide the final stage of a line driver to provide the current. One approach is the use of a source output, and the second approach is the use of a drain output. FIGS. 1 and 2 respectively illustrate the two circuit configurations for a final stage with a source output, and for a final stage with a drain output.
The circuit of FIG. 1 includes a source output stage in which a first branch comprises a first pair of CMOS transistors formed by a first NMOS transistor 1 and a first PMOS transistor 2. The NMOS transistor 1 has a drain terminal connected to its gate terminal, and the drain is also connected to the supply voltage Vdd. A current source 3 is interposed between the supply voltage Vdd and the NMOS transistor 1. The source terminal of the transistor 1 is connected to the source terminal of the PMOS transistor 2. The PMOS transistor 2 has a drain terminal connected to its gate terminal, and the drain is also connected to ground. A current source 4 is interposed between ground and the PMOS transistor 2.
A second branch of the output stage comprises a pair of MOS transistors 5 and 6, respectively of the n-type and of the p-type. The pair of MOS transistors 5, 6 are series-connected between the supply voltage Vdd and ground. Respective gate terminals of the pair of MOS transistors 5, 6 are connected to respective gate terminals of the transistors 1, 2.
With this configuration, the quiescent-state (or standby) current level is controlled accurately since there is a 1:1 mirroring ratio between the first branch and the second branch. Therefore, the current in the second branch is equal to the current flowing in the first branch. However, this type of output stage imposes a drawback of not providing an adequate output dynamic range for an input signal Vin having a large peak-to-peak amplitude. The output dynamic range is limited to Vdd-2*Vth-4*Vov. Vth is the threshold voltage of the MOS transistors of the second branch, and Vov is the overdrive voltage. Accordingly, this approach is not acceptable when one wishes to have, as in this case, a wide output dynamic range (working with low supply voltages on the order of 3-3.3 volts).
The circuit of FIG. 2 includes a drain output comprising a pair of MOS transistors of the p-type and of the n-type, respectively designated by the reference numerals 7 and 8. The pair of MOS transistors 7, 8 are series-connected between the supply voltage Vdd and ground. These transistors 7, 8 operate in an opposite manner since the output dynamic range is high (equal to Vdd-2*Vov), but the current level cannot be easily controlled unless complex control structures are implemented.